This is the input clock signal name used in the lfsr module.
This is the preset input name used in the lfsr module.
This is the terminal count name used in the lfsr module. The name is still used internally, even if the signal is not brought out.
This is the clock enable input name. It is not used if clock enable is not used.
The name for the shift register outputs.
This window is where most of the counter's parameters are. Use the radio buttons, text field and check boxes to configure your counter and then select the special menu, 'Generate Verilog Code'.
Adds signal 'clock enable' to synchronously disable the clock. Counting is inhibited by recirculating previous state of the register. The clock enable is not selected.
The counter has a clock enable to synchronously disable the clock. Counting is inhibited by recirculating the previous state of the shift register. Clock enable must be stable a set up time before the active edge of the clock.
Terminal count indicates count has concluded. It is selected to be used only internally and is not brought out of the module.
Terminal count indicates count has concluded. It is selected to be brought out of the module.
The output state of the shift register can be brought out of the module. It is currently selected not to do so.
The output state of the shift register can be brought out of the module.
The counter will preset itself at every terminal count. That is, it will produce a steady stream of pulses separated by count number of clocks. The counter is currently configured to one shot.
The counter will preset itself at every terminal count. That is, it will produce a steady stream of pulses separated by count clocks.
Counting stops after terminal count and will remain stopped until the counter is preset again. The counter is currently configured to be retriggerable.
Counting stops after terminal count and will remain stopped until the counter is preset again.
The counter changes state on the positive edge of the incoming clock.
The counter changes state on the negative edge of the incoming clock.
The counting is stopped synchronously when the clock enable input is low.
This selection is disabled since clock enable is not brought into the module.
The counting is stopped synchronously when the clock enable input is high.
The count sequence completion causes terminal count to go low for a clock cycle.
This selection is disabled since Terminal Count is currently not brought out of the module.
The count sequence completion causes terminal count to go high for a clock cycle.
The counter is synchronously set to a known starting state when the input preset is asserted high. Counting is stopped while preset is high.
The counter is synchronously set to a known starting state when the input preset is asserted low. Counting is stopped while preset is low.
Use AND (or NAND) logic to detect for terminal count. For very large counts, this will require large gate tree and an auxiliary counter may be an economical alternative. Current selection is to use an auxiliary counter.
Use AND (or NAND) logic to detect for terminal count. For very large counts, this will require large gate tree and an auxiliary counter may be an economical alternative.
Use an auxiliary counter to count the number of '1' bits shifted into the main shift register. The count of the auxiliary counter is the number of shift register stages in the larger counter. The current selection is to use combinatorial logic.
Use an auxiliary LFSR counter to count the number of '1' bits shifted into the main shift register. The count of the auxiliary counter is the number of shift register stages in the larger counter and it's terminal count serves as main terminal count.
Count is a decimal number from 2 to 2,147,483,648. It is the programmed number of clocks from preset to terminal count.
This saves the window contents to the file 'VLog preferences' located in the System preferences folder. The window is automatically closed after saving.
Test code is not generated for the module.
Test code is generated for the module. The test code uses standard incrementing counter to compare to the LFSR counter.
The designer's name is entered here. It is inserted into the comment field of the code module. Leave empty for no entry.
The company name is entered here. It is inserted into the comment field of the code module. Leave empty for no entry.
The project's name or title is entered here. It is inserted into the comment field of the code module. Leave empty for no entry.
This is a postive decimal number of units from the rising to falling edge of a symmetrical clock used in the test code.
This is a non-editable window displaying the temporary storage for cut, copy and paste operations.
This is an non-editable window for displaying help text. The text can be saved, printed and copied to the clipboard.
This is the window where the verilog code is displayed or the generated sequence. Contents in this window can be saved and printed.
